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XE88LC05 Data Sheet
XE88LC05
16 + 10 bit Data Acquisition Ultra Low-Power Microcontroller
General Description
The XE88LC05 is an ultra low-power microcontroller unit (MCU) associated with a versatile analog-to-digital converter (ADC) including a programmable offset and gain pre-amplifier (PGA) and digital-to-analog converters (DACs). XE88LC05 is available with on chip Multiple-Time-Programmable (MTP) Flash program memory and ROM.
Key product Features
* Low-power, high resolution ZoomingADC
* * * 0.5 to 1000 gain with offset cancellation up to 16 bits ADC up to 13 input multiplexer
* * * * * *
Buffered signal-DAC (up to 16 bits) Buffered bias-DAC (up to 10 mA drive) Low-voltage low-power controller operation
* * 2 MIPS at 2.4 V to 5.5 V supply voltage 300 A at 1 MIPS, 2.4 V to 5.5 V supply
Applications
* * * * * * * Internet connected appliances Portable, battery operated instruments Piezoresistive bridge sensors 4-20 mA bus sensors 0.5 - 4.5 V sensors HVAC control Motor control
22 kByte (8 kInstruction) MTP, 520 Byte RAM RC and crystal oscillators 5 reset, 18 interrupt, 8 event sources
Ordering Information
Reference
XE88LC05MI000 XE88LC05MI028 XE88LC05RI000 XE88LC05RI028
Memory type Temperature
MTP Flash MTP Flash ROM ROM -40C to 85C -40C to 85C -40C to 125C -40C to 125C
Package
die LQFP64 die LQFP64
cool solutions for short-range wireless connectivity
XEMICS SA, Switzerland. Tel: +41 32 720 5511 Fax: +41 32 720 5770 email: info@xemics.com web: www.xemics.com
Data Acquisition Microcontroller XE88LC05 1 Detailed Pin Description
Vreg Vss_Vreg Vss Vbat DAS_AO DAS_AI_m DAS_AI_p 59 57 55 53 DAS_Out 51 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 28 DAB_AO_m DAB_AO_p DAB_Out 30 DAB_AI_m DAB_AI_p 33 TEST AC_R(0) AC_R(1) AC_A(0) AC_A(1) AC_A(2) AC_A(3) AC_A(4) AC_A(5) AC_A(6) AC_A(7) AC_R(2) AC_R(3) OscIn OscOut RESET Vmult PA(0) PA(1) PA(2) PA(3) PA(4) PA(5) PA(6) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 PB(0) PB(1) PB(2) 20 PB(3) PB(4) 22 PB(5) PB(6) 63 61
N9K1444 9920
XE88LC05MI
XEMICS
packaging date
PA(7) PC(0) PC(1) PC(2) PC(3) PC(4) PC(5) PC(6) PC(7)
production lot identification device type
24 PB(7) DAB_R_p
26 DAB_R_m
Figure 1.1:
Pinout of the XE88LC05 in LQFP64 package
Pin Second function name
Position
Function name
PA(0)
Type
Description
Input of Port A/ Data input for MTP programming/ Counter A input Input of Port A/ Data clock for MTP programming/ Counter B input Input of Port A/ Counter C input/ Counter capture input Input of Port A/ Counter D input/ Counter capture input Input of Port A Input of Port A Input of Port A Input of Port A Input-Output of Port C Input-Output of Port C Input-Output of Port C Input-Output of Port C Input-Output of Port C Input-Output of Port C Input-Output of Port C Input-Output of Port C
1
Input
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
PA(1) PA(2) PA(3) PA(4) PA(5) PA(6) PA(7) PC(0) PC(1) PC(2) PC(3) PC(4) PC(5) PC(6) PC(7)
Input Input Input Input Input Input Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output
Table 1.1:
Pin-out of the XE88LC05 in LQFP64 (see Table "IO pins performances" on page 17 for drive capabilities of the pins)
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Pin Second function name
Position
Function name
PB(0) PB(1) PB(2) PB(3) PB(4) PB(5) PB(6) PB(7) DAB_R_p DAB_R_m DAB_Out DAB_AO_p DAB_AO_m DAB_AI_p DAB_AI_m VPP AC_R(3) AC_R(2) AC_A(7) AC_A(6) AC_A(5) AC_A(4) AC_A(3) AC_A(2) AC_A(1) AC_A(0) AC_R(1) AC_R(0) DAS_Out DAS_AI_p DAS_AI_m DAS_AO Vbat Vss Vss_Reg Vreg Vmult RESET Xout Xin -
Type
Description
Input-Output-Analog of Port B/ Data output for MTP programming/ PWM output Input-Output-Analog of Port B/ PWM output Input-Output-Analog of Port B Input-Output-Analog of Port B, Output pin of USRT Input-Output-Analog of Port B/ Clock pin of USRT Input-Output-Analog of Port B/ Data input or input-output pin of USRT Input-Output-Analog of Port B/ Emission pin of UART Input-Output-Analog of Port B/ Reception pin of UART Positive reference of bias DAC Negative reference of bias DAC Output of bias DAC Highest potential output of bias DAC buffer Lowest potential output of bias DAC buffer Positive input of bias DAC buffer Negative input of bias DAC buffer Spare pins to be connected to negative power supply Test mode/High voltage for MTP programming Spare pins to be connected to negative power supply Highest potential node for 2nd reference of ADC Lowest potential node for 2nd reference of ADC ADC input node ADC input node ADC input node ADC input node ADC input node ADC input node ADC input node ADC input node Highest potential node for 1st reference of ADC Lowest potential node for 1st reference of ADC Spare pins to be connected to negative power supply Output of signal DAC Positive input of signal DAC buffer Negative input of signal DAC buffer Output of signal DAC buffer Positive power supply Negative power supply, connected to substrate Digital negative power supply, must be equal to Vss Regulated supply Spare pins to be connected to negative power supply Pad for optional voltage multiplier capacitor Reset pin (active high) Connection to Xtal/ Peripheral clock for MTP programming Connection to Xtal/ CoolRISC clock for MTP programming Do not connect, or VSS
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47-50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Input/Output/Analog Input/Output/Analog Input/Output/Analog SOUT SCL SIN Tx Rx Input/Output/Analog Input/Output/Analog Input/Output/Analog Input/Output/Analog Input/Output/Analog Analog Analog Analog Analog Analog Analog Analog Not connected Special Not connected Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Not connected Analog Analog Analog Analog Power Power Power Analog Not connected Analog Input Analog/Input Analog/Input -
TEST/Vhigh
VDD
OscOut/ptck OscIn/crck
Table 1.1:
Pin-out of the XE88LC05 in LQFP64 (see Table "IO pins performances" on page 17 for drive capabilities of the pins)
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Data Acquisition Microcontroller XE88LC05 2 Absolute maximum ratings
Stresses beyond these listed in this chapter may cause permanent damage to the device. No functional operation is implied at or beyond these conditions. Exposure to these conditions for an extended period may affect the device reliability.
Parameter
VBAT with respect to VSS Input voltage on any input pin Storage temperature Storage temperature for programmed MTP devices
Value
-0.3V to 6.0V VSS-0.3V to VBAT+0.3V -55C to 125C -40C to 85C
Remarks
1 1
Table 2.1: Note:
Absolute maximum ratings 1) For unprogrammed MTP devices. Blocking bits and software must be rewritten in MTP devices if storage temperature exceedes storage temperature for programmed devices. These devices are ESD sensitive. Although these devices feature proprietary ESD protection structures, permanent damage may occur on devices subjected to high energy electrostatic discharges. Proper ESD precautions have to be taken to avoid performance degradation or loss of functionality.
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Data Acquisition Microcontroller XE88LC05 3 Electrical Characteristics
All specification are -40C to 85C unless otherwise noted. ROM operates up to 125C.
Operation conditions
ROM version Power supply MTP version Operating speed 2.4 V to 5.5 V Instruction cycle any instruction CPU running at 1 MIPS CPU running at 32 kHz on Xtal, RC off CPU halt, timer on Xtal, Current requirement RC off CPU halt, timer on Xtal, RC ready CPU halt, Xtal off timer on RC at 100 kHz CPU halt, ADC 16 bits at 4 kHz CPU halt, ADC 12 bits at 4 kHz, PGA gain 100 CPU at 1 MIPS, ADC 12 bits and DAC 10 bits at 4 kHz CPU at 1 MIPS, ADC 12 bits and DAC 10 bits Current requirement at 4 kHz, PGA gain 10 CPU at 1 MIPS, ADC 12 bits and DAC 10 bits at 4 kHz, PGA gain 100 CPU at 1 MIPS, ADC 12 bits and DAC 10 bits at 4 kHz, PGA gain 1000 Voltage level detection Prog. voltage Erase time MTP Flash instruction memory Write/Erase cycles Data retention
min
2.4 2.4 0.032
typ
max
5.5 5.5 2
Unit
V V MHz ns uA
Remarks
500 310
7 1
10
uA
1
1
uA
1
1.7
uA
1
1.4
uA
1
190
uA
4,6
460
uA
4,6
670
uA
3,4,6
790
uA
3,4,6
940
uA
3,4,6
1100
uA
3,4,6
15 10.3 0.2 10 10 10.8 1 100
uA V s year
8 5 2
Table 3.1: Note:
Specifications and current requirement of the XE88LC05 1) Power supply: 2.4 V - 5.5 V, temperature is 27C. 2) Temperature < 85C, < 10 erase cycles. 3) Output not loaded. 4) Current requirement can be divided by a factor of 2 or 4 by reducing the speed accordingly. 5) More cycles possible during development, with restraint retention
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Data Acquisition Microcontroller XE88LC05
6) Power supply: 3.0V, at 27C; see chapter Power Consumption on page 30 for variation of current with voltage and clock speed variation 7) With 2 MHz clock, all instructions are using exactly 1 clock cycle 8) Longer erase time may degrade retention
4 CPU
The XE88LC05 CPU is a low power RISC core. It has 16 internal registers for efficient implementation of the C compiler. Its instruction set is made of 35 generic instructions, all coded on 22 bits, with 8 addressing modes. All instructions are executed in one clock cycle, including conditional jumps and 8x8 multiplication.
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Data Acquisition Microcontroller XE88LC05 5 Memory organization
The CPU uses a Harvard architecture, so that memory is organized in two separated fields: program memory and data memory. As both memories are separated, the central processing unit can read/write data at the same time it loads an instruction. Peripherals and system control registers are mapped on data memory space. Program memory is made in one page. Data is made of several 256 bytes pages.
Program address bus
Data address bus
0h1FFF / 01hBFF
0h027F RAM 512 Bytes 0h0080 Peripherals
Program memory 8k instructions MTP or 6k instructions ROM
CPU
0h0000 22 bits wide Figure 5.1: Memory organization
CPU Instruction pipeline registers
0h0010 LP RAM 8 bits wide 0h0000
5.1 Program memory
The program memory is implemented as Multiple Time Programmable (MTP) Flash memory or ROM. The power consumption of MTP memory is linear with the access frequency (no significant static current). Size of the MTP Flash memory is 8192 x 22 bits (= 22 kBytes) Size of the ROM memory is 6144 x 22 bits (= 17 kBytes)
block
MTP ROM
size
8192 x 22 6144 x 22
address
H0000 - H1FFF H0000 - H1BFF
Table 5.1:
Program addresses for MTP or ROM memory
5.2 Data memory
The data memory is implemented as static Random-Access Memory (RAM). The RAM size is 512 x 8 bits plus 8 low power RAM bytes that require very low current when addressed. Programs using the low-power RAM instead of RAM will use even less current.
block
LP RAM RAM
size
8x8 512 x 8
address
H0000 - H0007 H0080 - H027F
Table 5.2:
RAM addresses
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6 Registers list
Left column include register name and address. Right columns include bit name, access (r: read, r0: always 0 when read, w: write, c: cleared by writing any value, c1: cleared by writing 1), and reset status (0 or 1) and signal. Empty bits are reserved for future use and should not be written, neither should their read value be used for any purpose as it may change without notice.
6.1 Peripherals mapping
block
LP RAM System control Port A Port B Port C Reserved MTP Event Interrupts control reserved UART Counters Zooming ADC Reserved DACs Other (VLD) RAM1 RAM2 RAM3
size
8x8 16x8 8x8 8x8 4x8 4x8 4x8 4x8 8x8 8x8 8x8 8x8 8x8 12x8 8x8 4x8 128x8 256x8 128x8
address
H0000-H0007 H0010-H001F H0020-H0027 H0028-H002F H0030-H0033 H0034-H0037 H0038-H003B H003C-H003F H0040-H0047 H0048-H004F H0050-H0057 H0058-H005F H0060-H0067 H0068-H0073 H0074-H007B H007C-H007F H0080 - H00FF H0100 - H01FF H0200 - H027F
Page
Page 0
Page 1 Page 2
Table 6.1:
Peripherals addresses
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Data Acquisition Microcontroller XE88LC05
6.2 Resets
The reset source name is simplified in the following registers description. Name mapping is in the next table.
reset source
resetsystem resetSynch resetPOR resetCold resetPad resetPconf resetSleep
name in this document
global
cold pconf sleep
Table 6.2:
Reset signal name mapping
6.3
Low power RAM
Low power RAM is a small additionnal RAM area with extremely low power requirement.
7 6 5 4 3 2 1 0
Name Address h0000 h0001 h0002 h0003 h0004 h0005 h0006 h0007
rw rw rw rw rw rw rw rw
rw rw rw rw rw rw rw rw
rw rw rw rw rw rw rw rw
rw rw rw rw rw rw rw rw
rw rw rw rw rw rw rw rw
rw rw rw rw rw rw rw rw
rw rw rw rw rw rw rw rw
rw rw rw rw rw rw rw rw
Table 6.3:
Low power RAM
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6.4 System, oscillators, prescaler and watchdog
7
SleepEn rw, 0 por Sleep w, 0 cold CpuSel rw, 0 sleep
Name Address
RegSysCtrl
6
EnResPConf rw, 0 cold ResPor r, 0 ExtClk r, 0 cold
5
EnBus-Error rw, 0 cold ResBusError rc, 0 cold EnExtClk rw, 0 cold
4
EnResWD rw, 0 cold ResWD rc, 0 cold BiasRC rw, 1 cold
3
2
1
0
h0010, type 1
RegSysReset
ResPortA rc, 0 cold ColdXtal r, 1 sleep RCOnPA0 rw, 0 sleep special
ResPad-Deb rc, 0 cold ColdRC r, 1 sleep DebFast rw, 0 sleep special
ResPad rc, 0 cold EnableXtal rw, 0 sleep OutputCkXtal rw, 0 sleep special EnableRC rw, 1 sleep OutputCkCPU rw, 0 sleep special ResPre ClearLowPrescal (*)
h0011, type 1
RegSysClock
h0012, type 1
RegSysMisc
h0013, type 1
RegSysWD
WatchDog(3) WatchDog(2) WatchDog(1) WatchDog(0)
h0014
RegSysPre0
h0015
RegSysRCTrim1 RCFreqRange rw, 0 cold RCFreqFine(5) rw, 1 cold RCFreqFine(4) rw, 0 cold RCFreqCoarse(3) rw, 0 cold RCFreqFine(3) rw, 0 cold RCFreqCoarse(2) rw, 0 cold RCFreqFine(2) rw, 0 cold RCFreqCoarse(1) rw, 0 cold RCFreqFine(1) rw, 0 cold
h001B
RegSysRCTrim2
w, 0 cold RCFreqCoarse(0) rw, 0 cold RCFreqFine(0) rw, 0 cold
h001C
Table 6.4:
System control registers
6.5
PortA
7
PAIn(7) r PADeb(7) rw, 0 pconf PAEdge(7)
Name Address
RegPAIn
6
RegPAIn(6) r PADeb(6) rw, 0 pconf PAEdge(6)
5
PAIn(5) r PADeb(5) rw, 0 pconf PAEdge(5)
4
PAIn(4) r PADeb(4) rw, 0 pconf PAEdge(4)
3
PAIn(3) r PADeb(3) rw, 0 pconf PAEdge(3)
2
PAIn(2) r PADeb(2) rw, 0 pconf PAEdge(2)
1
PAIn(1) r PADeb(1) rw, 0 pconf PAEdge(1)
0
PAIn(0) r PADeb(0) rw, 0 pconf PAEdge(0)
h0020
RegPADebounce
h0021
RegPAEdge
h0022
RegPAPullup
rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global PAPullUp(7) PAPullUp(6) PAPullUp(5) PAPullUp(4) PAPullUp(3) PAPullUp(2) PAPullUp(1) PAPullUp(0) rw, 0 pconf PARes0(7) rw, 0 pconf PARes0(6) rw, 0 pconf PARes0(5) rw, 0 pconf PARes0(4) rw, 0 pconf PARes0(3) rw, 0 pconf PARes0(2) rw, 0 pconf PARes0(1) rw, 0 pconf PARes0(0)
h0023, type 1
RegPARes0
h0024
RegPARes1
rw, 0 global rw, 0 global PARes1(7) PARes1(6) rw, 0 global rw, 0 global
rw, 0 global rw, 0 global rw, 0 global PARes1(5) PARes1(4) PARes1(3) rw, 0 global rw, 0 global rw, 0 global
rw, 0 global rw, 0 global rw, 0 global PARes1(2) PARes1(1) PARes1(0) rw, 0 global rw, 0 global rw, 0 global
h0025
Table 6.5:
Port A registers
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Data Acquisition Microcontroller XE88LC05
6.6 PortB
7
PBOut(7) rw, 0 pconf PBIn(7) r PBDir(7) rw, 0 pconf PBOpen(7) rw, 0 pconf rw, 0 pconf
Name Address
RegPBOut
6
PBOut(6) rw, 0 pconf PBIn(6) r PBDir(6) rw, 0 pconf PBOpen(6) rw, 0 pconf rw, 0 pconf
5
PBOut(5) rw, 0 pconf PBIn(5) r PBDir(5) rw, 0 pconf PBOpen(5) rw, 0 pconf rw, 0 pconf
4
PBOut(4) rw, 0 pconf PBIn(4) r PBDir(4) rw, 0 pconf PBOpen(4) rw, 0 pconf rw, 0 pconf
3
PBOut(3) rw, 0 pconf PBIn(3) r PBDir(3) rw, 0 pconf PBOpen(3) rw, 0 pconf rw, 0 pconf PBAna(3) rw, 0 pconf
2
PBOut(2) rw, 0 pconf PBIn(2) r PBDir(2) rw, 0 pconf PBOpen(2) rw, 0 pconf rw, 0 pconf PBAna(2) rw, 0 pconf
1
PBOut(1) rw, 0 pconf PBIn(1) r PBDir(1) rw, 0 pconf PBOpen(1) rw, 0 pconf rw, 0 pconf PBAna(1) rw, 0 pconf
0
PBOut(0) rw, 0 pconf PBIn(0) r PBDir(0) rw, 0 pconf PBOpen(0) rw, 0 pconf rw, 0 pconf PBAna(0) rw, 0 pconf
h0028
RegPBIn
h0029
RegPBDir
h002A
RegPBOpen
h002B
RegPBPullup
PBPullUp(7) PBPullUp(6) PBPullUp(5) PBPullUp(4) PBPullUp(3) PBPullUp(2) PBPullUp(1) PBPullUp(0)
h002C
RegPBAna
h002D
Table 6.6:
Port B registers
6.7
PortC
7
PCOut(7) rw, 0 pconf PCIn(7) r PCDir(7) rw, 0 pconf
Name Address
RegPCOut
6
PCOut(6) rw, 0 pconf PCIn(6) r PCDir(6) rw, 0 pconf
5
PCOut(5) rw, 0 pconf PCIn(5) r PCDir) rw, 0 pconf
4
PCOut(4) rw, 0 pconf PCIn(4) r PCDir(4) rw, 0 pconf
3
PCOut(3) rw, 0 pconf PCIn(3) r PCDir(3) rw, 0 pconf
2
PCOut(2) rw, 0 pconf PCIn(2) r PCDir(2) rw, 0 pconf
1
PCOut(1) rw, 0 pconf PCIn(1) r PCDir(1) rw, 0 pconf
0
PCOut(0) rw, 0 pconf PCIn(0) r PCDir(0) rw, 0 pconf
h0030
RegPCIn
h0031
RegPCDir
h0032
Table 6.7:
Port C registers
6.8
MTP
7 6 5 4 3 2 1 0
Name Address
RegEEP
h0038
RegEEP1
rw rw special special
rw rw special special
rw rw special special
rw rw special special
rw rw special special
rw rw special special
rw rw special special
rw rw special special
h0039
RegEEP2
h003A
RegEEP3
h003B
Table 6.8:
MTP control registers
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6.9 Events
7
EvnCntA rc1, 0 global EvnEnCntA rw, 0 global r,1 global
Name Address
RegEvn
6
EvnCntC rc1, 0 global EvnEnCntC rw, 0 global r,1 global
5
EvnPre1 rc1, 0 global EvnEnPre1 rw, 0 global r,1 global
4
EvnPA(1) rc1, 0 global EvnEnPA(1) rw, 0 global r,1 global
3
EvnCntB rc1, 0 global EvnEnCntB rw, 0 global r,1 global
2
EvnCntD rc1, 0 global EvnEnCntD rw, 0 global r,1 global
1
EvnPre2 rc1, 0 global EvnEnPre2 rw, 0 global r,1 global EvnHigh r, 0 global
0
EvnPA(0) rc1, 0 global EvnEnPA(0) rw, 0 global r,1 global EvnLow r, 0 global
h003C
RegEvnEn
h003D
RegEvnPriority
EvnPriority(7) EvnPriority(6) EvnPriority(5) EvnPriority(4) EvnPriority(3) EvnPriority(2) EvnPriority(1) EvnPriority(0)
h003E
RegEvnEvn
h003F
Table 6.9:
Events control registers
6.10
Interrupts
7
IrqAc rc1, 0 global
Name Address
RegIrqHig
6
IrqPre1 rc1, 0 global
5
4
IrqCntA rc1, 0 global
3
IrqCntC rc1, 0 global IrqPre2 rc1, 0 global IrqPA(3) rc1, 0 global IrqEnCntC rw, 0 global IrqEnPre2 rw, 0 global IrqEnPA(3) rw, 0 global IrqPriority(3) r, 1 global
2
1
IrqUartTx rc1, 0 global
0
IrqUartRx rc1, 0 global IrqPA(0) rc1, 0 global
h0040
RegIrqMid
IrqPA(5) rc1, 0 global IrqPA(7) rc1, 0 global IrqEnAc rw, 0 global IrqPA(6) rc1, 0 global IrqEnPre1 rw, 0 global IrqEnPA(5) rw, 0 global IrqEnPA(7) rw, 0 global IrqPriority(7) r, 1 global IrqEnPA(6) rw, 0 global IrqPriority(6) r, 1 global IrqEnCntB rw, 0 global IrqPriority(5) r, 1 global IrqCntB rc1, 0 global
IrqPA(4) rc1, 0 global IrqCntD rc1, 0 global IrqEnCntA rw, 0 global IrqEnPA(4) rw, 0 global IrqEnCntD rw, 0 global IrqPriority(4) r, 1 global
IrqVld rc1, 0 global IrqPA(2) rc1, 0 global
IrqPA(1) rc1, 0 global
h0041
RegIrqLow
h0042
RegIrqEnHig
IrqEnUartTx rw, 0 global IrqEnVld rw, 0 global IrqEnPA(2) rw, 0 global IrqPriority(2) r, 1 global IrqHig r, 0 global IrqPriority(1) r, 1 global IrqMid r, 0 global IrqEnPA(1) rw, 0 global
IrqEnUartRx rw, 0 global IrqEnPA(0) rw, 0 global
h0043
RegIrqEnMid
h0044
RegIrqEnLow
h0045
RegIrqPriority
IrqPriority(0) r, 1 global IrqLow r, 0 global
h0046
RegIrqIrq
h0047
Table 6.10:
Interrupts control registers
6.11
USRT
7 6 5 4 3 2 1 0
UsrtSin rw, 1 global UsrtScl rw, 1 global UsrtWaitS0 r, 0 global UsrtEnWaitUsrtEnWaitS0 Cond1 rw, 0 global rw, 0 global UsrtEnable rw, 0 global UsrtData r UsrtEdgeScl r, 0 global
Name Address
RegUsrtSin
h0048
RegUsrtScl
h0049
RegUsrtCtrl
h004A
RegUsrtData
h004D
RegUsrtEdgeScl
h004E
Table 6.11:
USRT control registers
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6.12 UART
7
UartEcho rw, 0 global SelXtal rw, 0 global UartTx(7) rw, 0 global
Name Address
RegUartCtrl
6
UartEnRx rw, 0 global
5
UartEnTx rw, 0 global
4
UartXRx rw, 0 global
3
UartXTx rw, 0 global
2
UartBR(2) rw, 1 global UartPM rw, 0 global UartTx(2) rw, 0 global
1
UartBR(1) rw, 0 global UartPE rw, 0 global UartTx(1) rw, 0 global UartTxBusy r, 0 global
0
UartBR(0) rw, 1 global UartWL rw, 1 global UartTx(0) rw, 0 global UartTxFull r, 0 global UartRx(0) r UartRxFull r
h0050
RegUartCmd
h0051
RegUartTx
UartWakeup UartRCSel(2) UartRCSel(1) UartRCSel(0) rw, 0 global rw, 0 global rw, 0 global rw, 0 global UartTx(6) rw, 0 global UartTx(5) rw, 0 global UartTx(4) rw, 0 global UartTx(3) rw, 0 global
h0052
RegUartTxSta
h0053
RegUartRx UartRx(7) r UartRx(6) r UartRx(5) r UartRxSErr r UartRx(4) r UartRxPErr r UartRx(3) r UartRxFErr r UartRx(2) r UartRxOErr c
UartRx(1) r UartRxBusy r
h0054
RegUartRxSta
h0055
Table 6.12:
UART control registers
6.13
Counters
7
CounterA(7) rw CounterB(7) rw CounterC(7) rw CounterD(7) rw CntDSel(1) rw rw CapSel(1) rw, 0 global
Name Address
RegCntA
6
CounterA(6) rw CounterB(6) rw CounterC(6) rw CounterD(6) rw CntDSel(0) rw rw CapSel(0) rw, 0 global
5
CounterA(5) rw CounterB(5) rw CounterC(5) rw CounterD(5) rw CntCSel(1) rw rw CapFunc(1) rw, 0 global
4
CounterA(4) rw CounterB(4) rw CounterC(4) rw CounterD(4) rw CntCSel(0) rw rw rw, 0 global
3
CounterA(3) rw CounterB(3) rw CounterC(3) rw CounterD(3) rw CntBSel(1) rw rw rw CntDEnable rw, 0 global
2
CounterA(2) rw CounterB(2) rw CounterC(2) rw CounterD(2) rw CntBSel(0) rw CascadeAB rw rw CntCEnable rw, 0 global
1
CounterA(1) rw CounterB(1) rw CounterC(1) rw CounterD(1) rw CntASel(1) rw CntPWM1 rw, 0 global rw CntBEnable rw, 0 global
0
CounterA(0) rw CounterB(0) rw CounterC(0) rw CounterD(0) rw CntASel(0) rw CntPWM0 rw, 0 global rw CntAEnable rw, 0 global
h0058
RegCntB
h0059
RegCntC
h005A
RegCntD
h005B
RegCntCtrlCk
h005C
RegCntConfig1
CntDDownUp CntCDownUp CntBDownUp CntADownUp CascadeCD
h005D
RegCntConfig2
CapFunc(0) PWM1Size(1) PWM1Size(0) PWM0Size(1) PWM0Size(0)
h005E
RegCntOn
h005F
Table 6.13:
Counters control registers
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Data Acquisition Microcontroller XE88LC05
6.14 Acquisition chain
7
AdcOutL(7) r AdcOutM(7) r Start r0w, 0 global rw, 1 global Fin(1) rw, 0 global Pga1Gain rw, 0 global
Name Address
RegAcOutLsb
6
AdcOutL(6) r AdcOutM(6) r NelConv(1) rw, 0 global rw, 1 global Fin(0) rw, 0 global Pga3Gain(6) rw, 0 global Pga3Off(6) rw, 0 global
5
AdcOutL(5) r AdcOutM(5) r NelConv(0) rw, 1 global rw, 1 global Pga2Gain(1) rw, 0 global Pga3Gain(5) rw, 0 global Pga3Off(5) rw, 0 global AMux(4) rw, 0 global
4
AdcOutL(4) r AdcOutM(4) r OSR(2) rw, 0 global rw, 1 global Pga2Gain(0) rw, 0 global Pga3Gain(4) rw, 0 global Pga3Off(4) rw, 0 global AMux(3) rw, 0 global
3
AdcOutL(3) r AdcOutM(3) r OSR(1) rw, 1 global Enable(3) rw, 0 global Pga2Off(3) rw, 0 global Pga3Gain(3) rw, 1 global Pga3Off(3) rw, 0 global AMux(2) rw, 0 global
2
AdcOutL(2) r AdcOutM(2) r OSR(0) rw, 0 global Enable(2) rw, 0 global Pga2Off(2) rw, 0 global Pga3Gain(2) rw, 1 global Pga3Off(2) rw, 0 global AMux(1) rw, 0 global
1
AdcOutL(1) r AdcOutM(1) r Cont rw, 0 global Enable(1) rw, 0 global Pga2Off(1) rw, 0 global Pga3Gain(1) rw, 0 global Pga3Off(1) rw, 0 global AMux(0) rw, 0 global
0
AdcOutL(0) r AdcOutM(0) r
h0060
RegAcOutMsb
h0061
RegAcCfg0
h0062
RegAcCfg1
IbAmpADC(1) IbAmpAdc(0) IbAmpPga(1) IbAmpPga(0)
Enable(0) rw, 1 global Pga2Off(0) rw, 0 global Pga3Gain(0) rw, 0 global Pga3Off(0) rw, 0 global VMux rw, 0 global
h0063
RegAcCfg2
h0064
RegAcCfg3
h0065
RegAcCfg4
h0066
RegAcCfg5 Busy r, 0 global
Def wr0
h0067
Table 6.14:
Acquisition chain control registers
6.15
DACs
7 6 5 4 3 2 1 0
Name Address
RegDasInLsb
DasInLSB(7) DasInLSB(6) DasInLSB(5) DasInLSB(4) DasInLSB(3) DasInLSB(2) DasInLSB(1) DasInLSB(0) w w w w w w w w DasInMSB(7) DasInMSB(6) DasInMSB(5) DasInMSB(4) DasInMSB(3) DasInMSB(2) DasInMSB(1) DasInMSB(0) w NSOrder(1) rw, 0 global w NSOrder(0) rw, 0 global w w w w w CodeIMax(2) CodeIMax(1) CodeIMax(0) DasEnable(1) DasEnable(0) rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global BW rw, 0 global DabIn(1) w Dab1Enable(1) rw, 0 global w Fin rw, 0 global Inv rw, 0 global DabIn(0) w Dab1Enable(0) rw, 0 global
h0074
RegDasInMsb
h0075
RegDasCfg0
h0076
RegDasCfg1
h0077
RegDab1In DabIn(7) w DabIn(6) w DabIn(5) w DabIn(4) w DabIn(3) w DabIn(2) w
h0078
RegDab1Cfg
h0079
Table 6.15:
DACs control registers
6.16
Vmult and Vld registers
7 6 5 4 3 2
Enable rw, 0 global VldMult rw, 0 cold VldTune(2) rw, 0 cold VldIrq r, 0 global
Name Address
RegVmultCfg0
1
Fin(1) rw, 0 global VldTune(1) rw, 0 cold VldValid r, 0 global
0
Fin(0) rw, 0 global VldTune(0) rw, 0 cold VldEn rw, 0 global
h007C
RegVldCtrl
h007E
RegVldStat
h007F
Table 6.16:
Vmult and Vld control registers
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Data Acquisition Microcontroller XE88LC05 7 Peripherals
The XE88LC05 includes usual microcontroller peripherals and some other blocks more specific to low-voltage or mixed-signal operation. There are 3 parallel ports, one input port (A), one IO and analog port (B) with analog switching capabilities and one general purpose IO port (C). A watchdog is available, connected to a prescaler. Four 8-bit counters, with capture, PWM and chaining capabilities are available. The UART can handle transmission speeds as high as 115kbaud. Low-power low-voltage blocks include a voltage level detector, two oscillators (one internal 0.1-2 MHz RC oscillator and a 32 kHz crystal oscillator) and a specific regulation scheme that largely uncouples current requirement from external power supply (usual CMOS ASICs require much more current at 5.5 V than they need at 2.4 V. This is not the case for the XE88LC05). Analog blocks (ZoomingADC (acquisition path), bias DAC and signal DAC) are defined below. All these blocks operate on 2.4 - 5.5 V power supply range.
7.1 Counters
* * * * * 4 8-bit counters Daisy chain on 16 bits PWM on 8-16 bits Capture - compare on 16 bits Events and interrupts generation
7.2 Prescaler
* Interrupt generated with 8 millisecond or 1 second period for ultra low power hibernation mode
7.3 Watchdog
* 2 seconds watchdog
7.4 UART
* * * * * * * * * * full duplex operation with buffered receiver and transmitter. internal baud rate generator with programmable baud rate (300 - 115000 bauds). 7 or 8 bits word length. even, odd, or no-parity bit generation and detection 1 stop bit error receive detection: Start, Parity, Frame and Overrun receiver echo mode 2 interrupts (receive full and transmit empty) enable receive and/or transmit invert pad Rx and/or Tx
7.5 Xtal clock
The Xtal Oscillator operates with an external crystal of 32'768 Hz.
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Data Acquisition Microcontroller XE88LC05
symbol
f_clk32k st_x32k duty_clk32k fstab_1
description
nominal frequency oscillator start-up time duty cycle on the digital output relative frequency deviation from nominal, for a crystal with CL=8.2 pF and temperature between -40 and +85C
min
typ
32768 1 50
max
2 70 +300
unit
Hz s % ppm
comments
for full precision
30 -100
not included: crystal frequency tolerance and aging crystal frequency - temperature dependence
Table 7.1: Note:
Xtal oscillator specifications. Board layout recommendations for safer crystal oscillation and lower current consumption: Keep lines xtal_in and xtal_out short and insert a VSS line between them. Connect package of the crystal to VSS. No noisy or digital lines near xtal_in and xtal_out. Insert guards at VSS where needed.
7.6 RC oscillator
The RC Oscillator is always turned on at power-on reset and can be turned off after the optional Xtal oscillator has been started. The RC oscillator has two frequency ranges: sub-MHz (100KHz to 1MHz) and above-MHz (1MHz to max MCU frequency). Inside a range, the frequency can be tuned by software for coarse and fine adjustment.
Note:
No external component is required for the RC oscillator. The RC oscillator can be in 3 modes. In mode 1(RC on), the RC oscillator and its bias are on. In mode 2 (RC ready), the RC oscillator is off and the bias is on. In mode 3 (RC off), the RC oscillator and the bias are off. RC ready mode is a compromise between power consumption and start-up time.
Figure 7.1:
symbol
Fst range
RC frequencies programming example for low range (typical values)
description
frequency at start-up range selection
min
50 1
typ
80
max
110 10
unit
kHz
comments
at 27C multiplies Fst
Table 7.2:
RC specifications
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Data Acquisition Microcontroller XE88LC05
symbol
mult[3:0] tune[5:0] Tst Ost Twu Owu jit Tdf
description
coarse tuning range fine tuning range fine tuning step start-up time overshoot at start-up wakeup time overshoot at wakeup jitter rms temperature drift
min
1 0.65
typ
max
16 1.5
unit
comments
4 bits, multiplies Fst * range 6 bits, multiplies Fst * range * mult
1.4 30 3 2 0.1
2 50 50 5 50
% ms % ms %
o
bias current is off (RC off) bias current is off (RC off) bias current is on (RC ready) bias current is on (RC ready)
/oo
%/C
Table 7.2:
RC specifications
7.7 Parallel IO ports
* * * 8 bit input port A with interrupt, reset and event generation. 8 bit input-output-analog port B with analog switching capabilities. 8 bit input-output port C.
sym
description
Port A: low threshold limit Port A: high threshold limit output drop when sinking 1 mA output drop when sinking 8 mA output drop when sourcing 1 mA output drop when sourcing 8 mA Port A: low threshold limit Port A: high threshold limit output drop when sinking 1 mA output drop when sinking 8 mA output drop when sourcing 1 mA output drop when sourcing 8 mA pull-up, pull-down resistor
condition
min
typ
1 1.5
max
unit
V V V V V V V V V V V V kohm
Comments
Vbat = 2.4 V
0.4 0.4 2 3
Vbat = 5.0 V
0.4 0.4 150
50
Table 7.3:
IO pins performances
7.8 Voltage level detector
* * Can be switched off, on or simultaneously with CPU activities Generates an interrupt if power supply is below a pre-determined level
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Data Acquisition Microcontroller XE88LC05
The Voltage Level Detector monitors the state of the system battery. It returns a logical high value (an interrupt) in the status register if the supplied voltage drops below the user defined level.
symbol description min
Note 1
typ
max
unit
comments
trimming values: VldRange 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Note 2 Note 2 VldTune 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111
Vth
Threshold voltage
1.53 1.44 1.36 1.29 1.22 1.16 1.11 1.06 3.06 2.88 2.72 2.57 2.44 2.33 2.22 2.13 2.0 875 2.5 1350
V
TEOM TPW
duration of measurement Minimum pulse width detected
ms us
Table 7.4: Note:
Voltage level detector operation 1) Absolute precision of the threshold voltage is 10%. 2) This timing is respected in case the internal RC or crystal oscillators are selected. Refer to the clock block documentation in case the external clock is used.
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Data Acquisition Microcontroller XE88LC05 8 ZoomingADC
The fully differential acquisition chain is formed of a programmable gain (0.5 - 1000) and offset amplifier and a programmable speed and resolution ADC (example: 12 bits at 4 kHz, 16 bits at 1 kHz). It can handle inputs with very low full scale signal and large offsets. AC_R(0) AC_R(1) AC_R(2) AC_R(3) AC_A(0) AC_A(1) AC_A(2) AC_A(3) AC_A(4) AC_A(5) AC_A(6) AC_A(7) reference selection
ADC gain1 input selection gain2 offset2 gain3 offset3 mode output code
Figure 8.1:
Acquisition channel block diagram Input selection is made from 1 of 4 differential pair or 1 of seven single signal versus AC_A(0). Reference is chosen from the 2 differential references. The gain of each amplifier is programmed individually. Each amplifier is powered on and off on command to minimize the total current requirement. All blocks can be set to low frequency operation and lower their current requirement by a factor 2 or 4. The ADC can run continuously (end of conversion signalled by an interrupt, event or by pooling the ready bit), or it can be started on request.
8.1 PGA 1
symbol
GD1 GD_preci GD_TC fs Zin1 Zin1p VN1
description
PGA1 Signal Gain Precision on gain settings Temperature dependency of gain settings input sampling frequency Input impedance Input impedance for gain 1 Input referred noise
min
1 -5 -5 150 1500
typ
max
10 +5 +5 512
unit
% ppm/C kHz k k nV/ sqrt(Hz)
Comments
GD1 = 1 or 10
1 1 2
28.6
Table 8.1: Note:
PGA1 Performances 1) Measured with block connected to inputs through AMUX block. Normalized input sampling frequency for input impedance is 512 kHz. This figure has to be multiplied by 2 for fs = 256 kHz and 4 for fs = 128 kHz. 2) Input referred rms noise is 205 uV per input sample with gain = 1, 20.5 uV with gain = 10. This corresponds to 28.6 nV/sqrt(Hz) for fs = 512 kHz and gain = 10.
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Data Acquisition Microcontroller XE88LC05
8.2 PGA2
sym
GD2 GDoff2 GDoff2_step GD_preci GD_TC fs Zin2 VN2
description
PGA2 Signal Gain PGA2 Offset Gain GDoff2(code+1) - GDoff2(code) Precision on gain settings Temperature dependency of gain settings Input sampling frequency Input impedance Input referred noise
min
1 -1 0.18 -5 -5 150
typ
max
10 1 0.22 +5 +5 512
unit
FS % ppm/C kHz k nV/ sqrt(Hz)
Comments
GD2 = 1, 2, 5 or 10
0.2
valid for GD2 and GDoff2
1 2
47.5
Table 8.2: Note:
PGA2 Performances 1) Measured with block connected to inputs through AMUX block. Normalized input sampling frequency for input impedance is 512 kHz. This figure has to be multiplied by 2 for fs = 256 kHz and 4 for fs = 128 kHz. 2) Input referred rms noise is 340 uV per input sample with gain = 1, 34 uV with gain = 10.This corresponds to 47.5 nV/sqrt(Hz) for fs = 512 kHz and gain = 10.
8.3 PGA3
sym
GD3 GDoff3 GD3_step GDoff3_step GD_preci GD_TC fs Zin3 VN3
description
PGA3 Signal Gain PGA3 Offset Gain GD3(code+1) - GD3(code) GDoff2(code+1) - GDoff2(code) Precision on gain settings Temperature dependency of gain settings Input sampling frequency Input impedance Input referred noise
min
0 -5 0.075 0.075 -5 -5
typ
max
10 5 0.085 0.085 +5 +5 512
unit
FS % ppm/C kHz k
Comments
0.08 0.08
valid for GD3 and GDoff3
150 51.0
1 2
nV/ sqrt(Hz)
Table 8.3: Note:
PGA3 Performances 1) Measured with block connected to inputs through AMUX block. Normalized input sampling frequency for input impedance is 512 kHz. This figure has to be multiplied by 2 for fs = 256 kHz and 4 for fs = 128 kHz. 2) Input referred rms noise is 365 uV per imput sample with gain = 1, 36.5 uV with gain = 10. This corresponds to 51.0 nV/sqrt(Hz) for fs = 512 kHz.
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Data Acquisition Microcontroller XE88LC05
8.4 Analog to digital converter (ADC)
The whole analog to digital conversion sequence is basically made of an initialisation, a set of Nelconv elementary incremental conversions and finally a termination phase(NumCONV is set by 2 bits on RegACCfg0). The result is a mean of the results of the elementary conversions.
input sample
12
smax 1 2
smax
12
smax
START conversion index
1st elementary conversion 1
2nd elementary conversion 2
elementary conversion NumConv-1
elementary conversion NumConv
END
Figure 8.2:
Conversion sequence. smax is the oversampling rate.
Note: NumCONV elementary conversions are performed, each elementary conversion being made of smax input samples. NumCONV = 2NELCONV smax = 8*2OSR During the elementary conversions, the operation of the converter is the same as in a sigma delta modulator. During one conversion sequence, the elementary conversions are alternatively performed with direct and crossed PGA-ADC differential inputs, so that when two elementary conversions or more are performed, the offset of the converter is cancelled.
Some additional clock cycles (NINIT+NEND) clock cycles are used to initiate and terminate the conversion properly.
8.5 ADC performances
sym
VINR Resol NResol DNL INL fs smax NUMCONV Ninit Nend
description
Input range Resolution Numerical resolution Differential non-linearity Integral non-linearity sampling frequency Oversampling Ratio Number of elementary conversions in incremental mode Number of periods for incremental conversion initialization Number of periods for incremental conversion termination
min
-0.5 6 -0.1 -3 10 8 1
typ
max
0.5 16 16 0.1 2 512 1024 8 5 5
unit
Vref bits bits LSB LSB kHz -
Comments
3 LSB at 16 bits 2, LSB at 16 bits 1 1
Table 8.4: Note:
ADC Performances 1) Only powers of 2 2) INL is defined as the deviation of the DC transfer curve from the best fit straight line. This
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Data Acquisition Microcontroller XE88LC05
specification holds over 100% of the full scale. 3) NResol is the maximal readable resolution of the digital filter.
8.6
resolution
6 8 12 13 16 16 16
conditions
oversampling per conversion = 8 1 conversion (no offset rejection) oversampling per conversion = 16 1 conversion (no offset rejection) oversampling per conversion = 64 1 conversion (no offset rejection) oversampling per conversion = 64 2 conversions (offset rejection) oversampling per conversion = 256 1 conversion (no offset rejection) oversampling per conversion = 256 2 conversions (offset rejection) oversampling per conversion = 1024 8 conversion s(offset rejection)
input frequency conversion time output frequency
512 kHz 512 kHz 512 kHz 512 kHz 512 kHz 512 kHz 512 kHz 40 us 50 us 150 us 275 us 500 us 1 ms 16.5 ms 25 kHz 20 kHz 6.7 kHz 3.6 kHz 2 kHz 1 kHz 60 Hz
Table 8.5:
ADC performances examples
8.7 Linearity
To quantify linearity errors, Integral Non-Linearity (INL) and Differential Non-Linearity (DNL) were measured for the ADC alone and for gains of 1, 5, 10, 20, 100, 1000, and a resolution of 12 bits and 16 bits. INL is defined as the deviation (in LSB) of the DC transfer curve of each individual code from the best-fit straight line. This specification holds over the full scale. DNL is defined as the difference (in LSB) between the ideal (1 LSB) and measured code transitions for successive codes. INL and DNL are specified after gain and offset errors have been removed.
8.8 Integral Non-Linearity (INL) and Differential Non-Linearity (DNL) for 12-bit resolution
12 bits - ADC converter (No PGA; ADC only) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples
12 bits - ADC converter (No PGA; ADC only) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples
1.0
0.50
Integral Non-Linearity (INL) [LSB]
0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 500 1000 1500 2000 2500
Differential Non-L inearity (DNL [L B ) S]
0.40 0.30 0.20 0.10 0.00 -0.10 -0.20 -0.30 0 500 1000 1500 2000 2500
VIN [mV]
VIN [mV]
Figure 8.3:
NO GAIN (ONLY ADC), 12 bit ADC setting
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Data Acquisition Microcontroller XE88LC05
12 bits - ADC converter (GDtot = 1) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples
12 bits - ADC converter (GDtot = 1) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples
2.0
0.50
Integral Non-Linearity (INL) [LSB]
1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 0 500 1000 1500 2000 2500
INL
Differential Non-Linearity (DNL) [LSB]
0.40 0.30 0.20 0.10 0.00 -0.10 -0.20 -0.30 0 500 1000 1500 2000 2500
VIN [mV]
VIN [mV]
Figure 8.4:
GAIN=1, 12 bit ADC setting
12 bits - ADC converter (GDtot = 5) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples
12 bits - ADC c onve rte r (GDtot = 5) (ve rsion v5a )
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples
1.0
0.50
Differential Non-Linearity (DNL) [LSB]
Integral Non-Linearity (INL) [LSB]
0.40 0.30 0.20 0.10 0.00 -0.10 -0.20 -0.30
0.5 0.0 -0.5 -1.0 -1.5 0 100 200 300 400 500
0
100
200
300
400
500
VIN [mV]
VIN [mV]
Figure 8.5:
GAIN=5, 12 bit ADC setting
12 bits - ADC converter (GDtot = 10) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples
12 bits - ADC converter (GDtot = 10) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples
2.0
0.50
Integral Non-Linearity (INL) [LSB]
1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 0 50 100 150 200 250
Differential Non-Linearity (DNL) [LSB]
0.40 0.30 0.20 0.10 0.00 -0.10 -0.20 -0.30 -0.40 -0.50 0 50 100 150 200 250
VIN [mV]
VIN [mV]
Figure 8.6:
GAIN=10, 12 bit ADC setting
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Data Acquisition Microcontroller XE88LC05
12 bits - ADC converter (GDtot = 20) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples
12 bits - ADC converter (GDtot = 20) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples
0.8
0.60
Integral Non-Linearity (INL) [LSB]
0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 0 20 40 60 80 100 120
Differential Non-Linearity (DNL) [LSB]
0.40 0.20 0.00 -0.20 -0.40 -0.60 -0.80 0 20 40 60 80 100 120
VIN [mV]
VIN [mV]
Figure 8.7:
GAIN=20, 12 bit ADC setting
12 bits - ADC converter (GDtot = 100) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples
12 bits - ADC converter (GDtot = 100) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples
4.0
1.00
Integral Non-Linearity (INL) [LSB]
3.0 2.0 1.0 0.0 -1.0 -2.0 -3.0 -4.0 0 5 10 15 20 25
Differential Non-Linearity (DNL) [LSB]
0.50 0.00 -0.50 -1.00 -1.50 0 5 10 15 20 25
VIN [mV]
VIN [mV]
Figure 8.8:
GAIN=100, 12 bit ADC setting
12 bits - ADC converter (GDtot = 1000) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples
12 bits - ADC converter (GDtot = 1000) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples
6.0
2.0
Differential Non-L inearity (DNL [L B ) S]
0 5 10 15 20 25
Integral Non-Linearity (INL) [LSB]
4.0 2.0 0.0 -2.0 -4.0 -6.0
1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 0 5 10 15 20 25
10*VIN [mV]
10*V IN [mV]
Figure 8.9:
GAIN=1000, 12 bit ADC setting
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Data Acquisition Microcontroller XE88LC05
8.9 Integral Non-Linearity (INL) and Differential Non-Linearity (DNL) for 16-bit resolution
16 bits - ADC converter (No PGA; ADC only) (ve rsion v5a )
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples
16 bits - ADC c onve rter (No PGA; ADC only) (ve rsion v5a )
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples
3 2 1 0 -1 -2 -3 0 500 1000 1500 2000 2500
0.10
Differential Non-Linearity (DNL) [LSB]
Integral Non-Linearity (INL) [LSB]
0.05 0.00 -0.05 -0.10 -0.15 0 500 1000 1500 2000 2500
VIN [mV]
VIN [mV]
Figure 8.10:
NO GAIN (ONLY ADC), 16 bit ADC setting
16 bits - ADC converter (GDtot = 1) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples
16 bits - ADC converter (GDtot = 1) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples
25.0 15.0 10.0 5.0 0.0 -5.0 -10.0 -15.0 -20.0 -25.0 0 500 1000 1500 2000 2500
0.10
Differential Non-Linearity (DNL) [LSB]
Integral Non-Linearity (INL) [LSB]
20.0
0.08 0.06 0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 0 500 1000 1500 2000 2500
VIN [mV]
VIN [mV]
Figure 8.11:
GAIN=1, 16 bit ADC setting
16 bits - ADC converter (GDtot = 5) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples
16 bits - ADC converter (GDtot = 5) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples
10.0
0.15
Differential Non-Linearity (DNL) [LSB]
0 100 200 300 400 500
Integral Non-Linearity (INL) [LSB]
5.0 0.0 -5.0 -10.0 -15.0 -20.0
0.10 0.05 0.00 -0.05 -0.10 -0.15 0 100 200 300 400 500
VIN [mV]
VIN [mV]
Figure 8.12:
GAIN=5, 16 bit ADC setting
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Data Acquisition Microcontroller XE88LC05
16 bits - ADC converter (GDtot = 10) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples
16 bits - ADC converter (GDtot = 10) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples
30 20 10 0 -10 -20 -30 0 50 100 150 200 250
0.25
Differential Non-Linearity (DNL) [LSB]
Integral Non-Linearity (INL) [LSB]
0.20 0.15 0.10 0.05 0.00 -0.05 -0.10 -0.15 -0.20 -0.25 0 50 100 150 200 250
VIN [mV]
VIN [mV]
Figure 8.13:
GAIN=10, 16 bit ADC setting
16 bits - ADC converter (GDtot = 20) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples
16 bits - ADC converter (GDtot = 20) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples
10
0.6
Integral Non-Linearity (INL) [LSB]
8 6 4 2 0 -2 -4 -6 -8 -10 0 20 40 60 80 100 120
Differential Non-Linearity (DNL) [LSB]
0.4 0.2 0.0 -0.2 -0.4 -0.6 0 20 40 60 80 100 120
VIN [mV]
VIN [mV]
Figure 8.14:
GAIN=20, 16 bit ADC setting
16 bits - ADC converter (GDtot = 100) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples
16 bits - ADC converter (GDtot = 100) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples
40
0.8
Differential Non-Linearity (DNL) [LSB]
0 5 10 15 20 25
Integral Non-Linearity (INL) [LSB]
30 20 10 0 -10 -20 -30 -40
0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 5 10 15 20 25
VIN [mV]
VIN [mV]
Figure 8.15:
GAIN=100, 16 bit ADC setting
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Data Acquisition Microcontroller XE88LC05
16 bits - ADC converter (GDtot = 1000) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples
16 bits - ADC converter (GDtot = 1000) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples
80
2.0
Integral Non-Linearity (INL) [LSB]
60 40 20 0 -20 -40 -60 -80 0 5 10 15 20 25
Differential Non-Linearity (DNL) [LSB]
1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 0 5 10 15 20 25
10*VIN [mV]
10*VIN [mV]
Figure 8.16:
GAIN=1000, 16 bit ADC setting
The gain settings of each PGA stage for the plots of above figure are those of the table below.
PGA Gain GDTOT (V/V)
1 5 10 20 100 1000
PGA1 Gain GD1 (V/V)
1 1 10 10 10 10
PGA2 Gain GD2 (V/V)
bypassed 5 bypassed 2 10 10
PGA3 Gain GD3 (V/V)
bypassed bypassed bypassed bypassed bypassed 10
Table 8.6: Table 8.7:
Individual PGA gains for INL & DNL measurements
8.10 Noise
Ideally, a constant input voltage VIN should result in a constant output code. However, because of circuit noise, the output code may vary for a fixed input voltage. The figure shows the distribution for the ADC alone (PGA1, 2, and 3 bypassed) and of several configurations of the PGAs. Quantization noise is dominant in this case of ADC only, and, thus, the ADC thermal noise is negligible. One has to considere two points when computing final noise of the acquisition chain: * this is a type of amplifier (switched-cap with constant capacitive load) that maintains its output noise when changing the gain. Therefore input refered noise is lowered when the gain of an amplifier is increased. * the ADC is oversampled, and the number of samples taken lowers the thermal noise
Total input refered noise can be computed using the following equation: V n, out1 Vn, out2 V n, out3 ----------------- + --------------------------------- + ----------------------------------------------------- gain1 gain1 gain2 gain1 gain2 gain3 2 V n, in = ----------------------------------------------------------------------------------------------------------------------------------------------numconv smax
2 2 2
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Data Acquisition Microcontroller XE88LC05
Where Vn,outx is the rms output noise of amplifier x.
Amplifier
PGA1 PGA2 PGA3
Symbol
Vn,out1 Vn,out2 Vn,out3
Typical output noise per over-sample
205 340 365
Unit
uVrms uVrms uVrms
Typical output noise of ZoomingADC preamplifiers
ADC only
PGA1: 1 PGA2: 10 PGA3: off
PGA1: off PGA2: 1 PGA3: 10
PGA1: 10 PGA2: 10 PGA3: off
PGA1: 1 PGA2: 10 PGA3: 10
Figure 8.17:
Noise measured at the output of the ZoomingADC As one can see on the figures above, increase the gain of the first amplifier lowers the output noise for constant global gain. It also lowers sensitivity to temperature drift as offset is better compensated on first amplifier.
8.11 Gain Error and Offset Error
Gain error is defined as the amount of deviation between the ideal transfer function and the measured transfer function (with the offset error removed). The left figure shows gain error vs. temperature for different PGA gains. The curves are expressed in% of Full-Scale Range (FSR) normalized to 25C. Offset error is defined as the output code error for a zero volt input (ideally, output code = 0). The measured offset errors vs. temperature curves for different PGA gains are depicted in the right figure below. The output offset error, expressed in (LSB), is normalized to 25C.
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Data Acquisition Microcontroller XE88LC05
Output Offset Error [LSB]
0.2
100 80 60 40 20 0 -20 -40 1 5 20 100
Gain Error [% of FSR]
0.1 0.0 -0.1 -0.2 -0.3 -0.4 -50 -25 0 25 50 75 100 1 5 20 100
-50
-25
0
25
50
75
100
Temperature [C]
Temperature [C]
Figure 8.18:
Gain and offset error vs temperature for several gains, normalized to 25C, offset cancellation disabled. When the offset cancellation is enabled, the offset of PGA1 and ADC
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Data Acquisition Microcontroller XE88LC05
8.12 Power Consumption
Left figure below plots the variation of quiescent current consumption with supply voltage VDD, as well as the distribution between the 3 PGA stages and the ADC. As shown in the right figure, quiescent current consumption is not greatly affected by sampling frequency. It can be seen that the quiescent current varies by about 20% between 100kHz and 2MHz. Quiescent current consumption vs. temperature is shown in the second set of figures, showing a relative increase of nearly 40% between -45 and +85C.
800 700 Quiescent Current - IQ [ A] 600 500
800 750 700 650 600 550 500
2.5 3.0 3.5 4.0 4.5 5.0 5.5
PGA1, 2 & 3
Quiescent Current - IQ [ A]
Sampling Frequency fS : 500kHz
250kHz 62.5kHz
PGA1 & 2 only
400
PGA1 only
300 200
No PGAs, ADC only
100
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Supply Voltage - VDDA [V]
Supply Voltage - VDDA [V]
Figure 8.19:
Quiescent current versus supply voltage for different gains and clock speed (not using the PGA and ADC low power modes)
20 Relative Quiescent Current Change IQ / IQ,25C [%] 15 10 5 0 -5 -10 -15 -20 -25
-50 -25 0 25 50 75 100 125
900 Quiescent Current - IQ [ A] 850 800 750 700 650 600 550 500
-50 -25 0 25 50 75 100 125
Temperature [C]
Temperature [C]
Figure 8.20:
Absolute and (b) relative change in quiescent current consumption vs. temperature
Supply
VDD = 5V VDD = 3V
ADC
250 190
PGA1
165 150
PGA2
130 120
PGA3
175 160
TOTAL
720 620
Unit
A A
Table 8.8:
Typical quiescent current distributions in acquisition chain (n = 16 bits, fS = 500kHz)
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Data Acquisition Microcontroller XE88LC05
Relative Quiescent Current Change IQ / IQ,2MHz [%]
0 500 1000 1500 2000 2500 3000 3500
850 Quiescent Current - IQ [ A] 800 750 700 650 600 550 500 Frequency - fRC [kHz]
15 10 5 0 -5 -10 -15 -20
0 500 1000 1500 2000 2500 3000 3500
Frequency - fRC [kHz]
Figure 8.21:
Absolute and (b) relative change in quiescent current consumption vs. clock speed
8.13 Power Supply Rejection Ratio
Figure below shows power supply rejection ratio (PSRR) at 3V and 5V supply voltage, and for various PGA gains. PSRR is defined as the ratio (in dB) of voltage supply change (in V) to the change in the converter output (in V). PSRR depends on both PGA gain and supply voltage VDD.
105 100 95
VDD=3V VDD=5V
PSRR [dB]
90 85 80 75 70 65 60 1 5 10 20 100
PGA Gain [V/V]
Figure 8.22:
Power supply rejection ratio (PSRR)
Supply VDD = 5V VDD = 3V
GAIN = 1 79 72
GAIN =5 78 79
GAIN = 10 100 90
GAIN = 20 99 90
GAIN =100 97 86
Unit dB dB
Table 8.9:
PSRR (n = 16 bits, VIN = VREF = 2.5V, fS = 500kHz)
8.14 Frequency Response
The incremental ADC of the XE88LC05 is an over-sampled converter with two main blocks: an analog modulator and a low-pass digital filter. The main function of the digital filter is to remove the quantization noise introduced by the modulator. As shown below, this filter determines the frequency response of the transfer function between the output of the ADC and the analog input VIN. Notice that the frequency axes are normalized to one elementary conversion
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Data Acquisition Microcontroller XE88LC05
period OSR/fS. The plots below also show that the frequency response changes with the number of elementary conversions NELCONV performed. In particular, notches appear for NELCONV S 2. These notches occur at:
f NOTCH (i ) =
i fS OSR N ELCONV (Hz)for i = 1,2,..., ( N ELCONV - 1)
and are repeated every fS/OSR. Information on the location of these notches is particularly useful when specific frequencies must be filtered out by the acquisition system. For example, consider a 5Hz-bandwidth, 16-bit sensing system where 50Hz line rejection is needed. Using the above equation and the plots below, we set the 4th notch for NELCONV = 4 to 50Hz, i.e. 1.25fS/OSR = 50Hz. The sampling frequency is then calculated as fS = 20.48kHz for OSR = 512. Notice that this choice yields also good attenuation of 50Hz harmonics.
Normalized Magnitude [-]
Normalized Magnitude [-]
1.2 1 0.8 0.6 0.4 0.2 0 0 1 2 3 4 Normalized Frequency - f *(OSR/fS) [-]
1.2 1 0.8 0.6 0.4 0.2 0 0 1 2 3 4 Normalized Frequency - f *(OSR/fS) [-]
NELCONV = 1
NELCONV = 2
Normalized Magnitude [-]
Normalized Magnitude [-]
1.2 1 0.8 0.6 0.4 0.2 0 0 1 2 3 4 Normalized Frequency - f *(OSR/fS) [-]
1.2 1 0.8 0.6 0.4 0.2 0 0 1 2 3 4 Normalized Frequency - f *(OSR/fS) [-]
NELCONV = 4
NELCONV = 8
Figure 8.23:
Frequency response: normalized magnitude vs. frequency for different NELCONV
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Data Acquisition Microcontroller XE88LC05 9 Digital to analog converters (DACs)
The XE88LC05 includes 2 DACs: a signal DAC and a bias DAC.
9.1 Bias DAC
The bias DAC is a low resolution (8 bits) DAC with a buffer perfectly adapted to sensor bridge bias. It can be used to bias a bridge in current (figure) or in voltage by choosing the pins connection.
Figure 9.1:
General block diagram of the bias DAC
The bias DAC itself is built of a series of resistors which two extremes are available outside the chip, so that one can connect it to an external source when the output of the DAC should not be ratiometric to the power supply.
9.2 The DAC of bias DAC
The DAC convertor is a resistive divider connected between pads DAB_R_m and DAB_R_p.
sym
wda tstep range INL DNL
description
min
typ
8
max
100 DAB_R_p 1 1
unit
bits ms LSB LSB
Comments
1 2 3 3
number of input bits step response DAC output range DAB_R_m integral non-linearity differential non-linearity
Table 9.1: Note:
DAC performances 1) Time to reach the final value within 5%. Node not charged. 2) In most cases DAB_R_m will be connected to VSS and DAB_R_p to VDD. 3) For DAB_R_m connected to VSS and DAB_R_p to VDD, VDD > 2.4 V.
9.3 The amplifier of bias DAC
The amplifier can be used in several configurations as for biasing a bridge in voltage or current. Application examples are given in application note AN8000.03.
sym
gain GBW
description
gain at DC gain bandwidth product
min
60 100
typ
max
unit
dB Hz
Comments
1 1
Table 9.2:
Amplifier performances
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Data Acquisition Microcontroller XE88LC05
sym
fm rl cl CMR OR outp vr voff noise isourc PSRR ibias ioff
description
phase margin resistive load capacitive load common mode input range output range outp pin voltage range offset integrated input noise max source current power supply rejection ratio quiescent bias current off current
min
60 300 vss vss+0.2 vss+2.3
typ
max
100000 1 vdd vdd-0.2 vdd 10 100 10
unit
ohm nF V V V mV uVrms mA dB uA uA
Comments
1 4,5
3
40 2 5 1
4 2 5
Table 9.2: Note:
Amplifier performances 1) For all possible combinations of resistive load and capacitive load. 2) At DC. 3) For voltage controlled bias control. For current controlled operation the voltage drop on the pMOS output transistor has to be less than 200mV at maximum current. 4) Short circuit protection at ~80mA. 5) This amplifier must be loaded for correct operation. Ibias is without load current.
9.4 Signal DAC
The signal DAC is build around a programmable DAC and a buffer. It can generate fast (up to 64 kHz) or high resolution (resolution up to 16 bits) output. The output can be controlled in current or voltage.
Figure 9.2:
General block diagram of the signal DAC
9.5 The amplifier of signal DAC
The amplifier can be used in several configurations. Therefore, it is not connected internally.
sym
gain GBW0 cl0 GBW1 cl1 fm rl SR CMR OR
description
gain at DC gain bandwidth product capacitive load gain bandwidth product capacitive load phase margin resistive load slew rate common mode input range output range
min
80 25
typ
max
unit
dB kHz nF kHz pF kohm kV/s V V
Comments
1 4 4 5 5 6 3 7
5 125 200 55 5 10 vss-0.2 vss+0.2
vdd-1.2 vdd-0.2
Table 9.3:
DAC signal amplifier performances
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Data Acquisition Microcontroller XE88LC05
sym
voff CMRR noise ibias ioff
description
offset common mode rejection integrated input noise quiescent bias current off current
min
60
typ
max
5 100 500 1
unit
mV dB uVrms uA uA
Comments
2
200
Table 9.3:
DAC signal amplifier performances
Note:
1) For the minimal resistive load and the maximal capacitive load 2) At DC 3) Short circuit protection at ~5mA. 4) GBW when the maximal load is cl0 and with the bit BW=0 5) GBW when the maximal load is cl1 and with the bit BW=1 6) In both cases BW=0 and BW=1 for the maximal capacitive load and the minimal resistive load. 7) For maximal load cl0, BW=0 and maximal resistive load rl
9.6 The DAC of signal DAC
The DAC of signal DAC can be used as a regular PWM DAC (NSorder set to 00), or a sigmadelta DAC (first or second order). The most efficient setting is the second order sigma-delta (NSorder set to 10), and this is the mode that we describe below. In order to function according to the following computation, it must be followed by a second order filter or larger with a given cut-off frequency.
Note:
The DAC output is ratiometric to power supply. It is highly important to avoid parasitic on power supply. It is recommended to have no heavy switching on output ports for precise DAC output. The D/A resolution in bits is given by (second order filter): resolution ( bit ) = - 0.226 + m + ( NSorder ( q - 2.65 ) ) with: m = PWM resolution in bits (4 .. 11)
m (PWM resolution in bits)
4 5 6 7 8 9 10 11
code_lmax
000 001 010 011 100 101 110 111
Table 9.4:
PWM resolution setting NSorder = order of the noise shaper = (0 .. 2)
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Data Acquisition Microcontroller XE88LC05
ns_order(1:0)
00 01 1x
Noise shaping order
0 1 2
Table 9.5:
Noise shaper order setting
q = ratio between the pulse repetition frequency (fs) and the cut-off frequency of the external low pass filter (fc) q = log 2( ( fs ) ( fc ) ) fs = PWM pulse repetition frequency ( frc ) ( fdiv ) fs = -----------------------------m 2
with frc the RC oscillator frequency; fdiv is the division factor of the frc as set by FIN.
FIN(1:0)
0 1
RC clock division factor: fdiv
1 2
Table 9.6:
RC clock division factor
Example:
f RC
=2MHz, FIN=1, m=4, fc=1kHz, NSorder=2 and therefore, the resolution is:
fs = 2 MHz 2 4 = 125kHz q = log 2 (125kHz / 1kHz ) = 6.96 resolution = -0.226 + 4 + 2 * (6.96 - 2.65) = 12.4bit
frc Hz
2'000'000 2'000'000 2'00'0000 2'000'000 2'000'000 2'000'000 2'000'000 2'000'000 2'000'000
fin
1 1 1 1 1 1 1 1 2
Settings m
4 4 4 4 4 5 6 11 4
fc Hz
4'000 2'000 1'000 500 250 1'000 1'000 250 1'000
ns
2 2 2 2 2 2 2 2 2
fs Hz
125'000 125'000 125'000 125'000 125'000 62'500 31'250 977 62'500
Performances q
4.97 5.97 6.97 7.97 8.97 5.97 4.97 1.97 5.97
resolution bits
8.4 10.4 12.4 14.4 16.0 11.4 10.4 9.4 10.4
Table 9.7:
Examples of resolution for different settings of the signal DAC and of the filter
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Data Acquisition Microcontroller XE88LC05 10 Physical description
10.1 LQFP64 package
Figure 10.1:
LQFP64 package, size in mm.
10.2 Die
pin 1
Figure 10.2:
Die. Chip size is 4.2 x 4.7mm2 for 0.3 mm thickness. Physical chip size and exact pad positioning can change without notification.
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Data Acquisition Microcontroller XE88LC05
10.2.1 Bonding pad location
Coordinates start with a point near to the bottom left border (with respect to above picture). X is horizontal, Y is vertical. Pad size is 85 x 85 um.
Symbol
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Pad
PA(0) PA(1) PA(2) PA(3) NC PA(4) PA(5) PA(6) PA(7) PC(0) PC(1) PC(2) PC(3) NC PC(4) PC(5) PC(6) PC(7) PB(0) PB(1) PB(2) PB(3) PB(4) NC PB(5) PB(6) PB(7) DAB_R_p DAB_R_n DAB_Out DAB_AO_p DAB_AO_n
X um
52.6 52.6 52.6 52.6 52.6 52.6 52.6 52.6 52.6 52.6 52.6 52.6 52.6 52.6 52.6 52.6 52.6 52.6 398.5 533.5 668.5 798.5 933.5 1063.5 1198.5 1328.5 1463.5 1593.5 1728.5 1858.5 2042.4 2683.3
Y um
4123.5 3908.5 3693.5 3478.5 3263.5 3048.5 2833.5 2618.5 2403.5 2188.5 1973.5 1758.5 1543.5 1328.5 1113.5 898.5 683.5 468.5 47.6 47.6 47.6 47.6 47.6 47.6 47.6 47.6 47.6 47.6 47.6 47.6 47.6 47.6
Symbol
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Pad
NC DAB_AI_p DAB_AI_n TEST AC_R(3) AC_R(2) AC_A(7) AC_A(6) AC_A(5) NC AC_A(4) AC_A(3) AC_A(2) AC_A(1) AC_A(0) NC AC_R(1) AC_R(0) DAS_Out DAS_AI_p DAS_AI_n DAS_AO Vbat Vss Vss_Vreg Vreg Vmult RESET OscOut NC OscIn Vss
X um
3363.5 3498.5 3628.5 3958.4 3958.4 3958.4 3958.4 3958.4 3958.4 3958.4 3958.4 3958.4 3958.4 3958.4 3958.4 3958.4 3958.4 3958.4 3628.5 3458.5 3293.5 3114.6 1923.5 1753.5 1588.5 1418.5 1252.9 1088.5 923.5 758.5 593.5 428.5
Y um
47.6 47.6 47.6 508.5 768.5 1028.5 1283.5 1543.5 1798.5 2058.5 2313.5 2573.5 2828.5 3088.5 3343.5 3603.5 3858.5 4118.5 4453.4 4453.4 4453.4 4453.4 4453.4 4453.4 4453.4 4453.4 4453.4 4453.4 4453.4 4453.4 4453.4 4453.4
Table 10.1:
Bonding pads location. Do not connect pads named NC. Pins 56, 57 and 64 must be connected to VSS.
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Data Acquisition Microcontroller XE88LC05 11 Contacting XEMICS
11.1 Web site:
http://www.xemics.com
11.2 XEMICS Headquarter, Sales for Europe and Asia
XEMICS SA Maladiere 71 CH-2007 Neuchatel Switzerland Tel: +41 32 720 5511 Fax: +41 32 720 5770 E-mail: info@xemics.com
11.3 Sales for USA
XEMICS USA Inc. 625 Ellis Street, #102 Mountain View, CA 94043 Phone: (650) 428 0600 Fax: (650) 938 1732 Toll free: 1-888-3XEMICS email: xemicsus@xemics.com
You will find more information about the XE88LC05 and other XEMICS products, as well as the addresses of our representatives and distributors for your region on www.xemics.com.
Copyright XEMICS, 2001 All rights are reserved. Reproduction whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
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